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W159B
Spread Spectrum System FTG for SMP Systems
Features
* Maximized EMI suppression using Cypress's spread spectrum technology (0.5% down spread) * Seven skew-controlled copies of CPU and 16.667-MHz synchronous APIC output * Two copies of fixed-frequency 33 MHz outputs * Four copies of 66 MHz fixed-frequency outputs * Two copies of CPU/2 outputs for synchronous memory reference * One copy of 48 MHz USB output * Two copies of 14.31818 MHz reference clock * Programmable to 133 or 100 MHz operation * Power management control pins for clock stop and shut down * Available in 56-pin SSOP
Key Specifications
Supply Voltages: ......... VDDQ3 = 3.3V5%VDDQ2 = 2.5V5% CPU Output Jitter: ...................................................... 200 ps CPUdiv2, 3V33, APIC Output Jitter: ........................... 250 ps CPU, 3V33 Output Edge Rate: .................................. >1 V/ns 48-MHz, 3V66, REF Output Jitter: .............................. 500 ps CPU0:6, CPUdiv2_0:1 Output Skew: ......................... 175 ps 3V66, APIC0:6, 3V33 Output Skew: ........................... 250 ps CPU to 3V66 Output Offset:.......... 0.0 to 1.5 ns (3V66 leads) 3V66 to 3V33 Output Offset:......... 1.5 to 3.0 ns (3V66 leads) CPU to APIC Output Offset:.............1 to 3.0 ns (CPU Leads) CPU to 3V33 Output Offsets:........1.0 to 4.0 ns (CPU Leads) Logic inputs, except SEL133/100#, have 100-k resistors. Table 1. Pin Selectable Frequency SEL133/100# 1 0 CPU0:6 (MHz) 133 MHz
[1] 100
pull-up
PCI 33.3 MHz 33.3 MHz
MHz
Block Diagram
X1 X2
Pin Configuration
2 REF_[0:1] 5 CPU_[0:4]
XTAL OSC
6W/4W#
2 CPU_[5:6]
2 SPREAD# /2 CPUdiv2_[0:1]
PLL 1
4 SEL133/100# /2//1.5 3V66_[0:3]
2 PWRDWN# /2 3V33_[0:1]
Power Down Logic
FIXAPIC#
5 /4 2 APIC_[5:6] APIC_[0:4]
APIC2 GND APIC1 APIC0 VDDQ2 X1 X2 VDDQ3 REF0/FIXAPIC#* REF1/TEST#* GND VDDQ3 GND 48MHz VDDQ3 3V66_0 3V66_1 VDDQ3 GND 3V66_2 3V66_3 VDDQ3 3V33_0 3V33_1 GND 6W/4W#* VDDQ3 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
APIC3 APIC4 VDDQ2 APIC5 APIC6 GND SPREAD#* VDDQ2 CPU0 CPU1 GND GND CPU2 CPU3 VDDQ2 VDDQ2 CPU4 CPU5 GND GND CPU6 VDDQ2 PWRDWN#* GND CPUdiv2_0 CPUdiv2_1 VDDQ2 SEL133/100#
PLL2
1
Note: 1. Pins denoted by * have a 250-k pull-up resistor. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
48MHz
W159B
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 10
www.SpectraLinear.com
W159B
Pin Definitions
Pin Name CPU0:6 Pin No. 48, 47, 44, 43, 40, 39, 36 Pin Type O Pin Description CPU Clock Outputs 0 through 6: These seven CPU clocks run at a frequency set by SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2. For 4-way SMP systems that do not require more than 5 CPU outputs, CPU5 and CPU6 can be disabled by asserting 6W/4W# during power-up. Synchronous Memory Reference Clock Output 0 through 1: Reference clock for Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output voltage swing is set by the voltage applied to VDDQ2. For systems using SDRAM, CPUdiv2_0:1 output can be disabled by tying VDDQ2 on pin 30 to GND. 33 MHz Fixed-Frequency Output: These are fixed-frequency outputs that can be used to drive PCI devices. 14.318 MHz Reference Clock Output/APIC Speed Select: During normal operations, this is a 3.3V 14.318-MHz reference output. During power-up, it is sampled to determine the operating frequency of APIC. If the sample is a "1," APIC will be set at CPU/4. If it is a "0," APIC will be fixed at 16.667 MHz. 14.318 MHz Reference Clock Output/Test Mode: During normal operations, this is a 3.3V 14.318-MHz reference output. The input is sampled at power-up to determine if the device should initialize for normal operations or test mode. Synchronous I/OAPIC Clock Outputs: APIC output frequency is determined by FIXAPIC# strapping. For 4-way SMP systems that do not require more than 5 APIC outputs, APIC5 and APIC6 can be disabled by asserting 4W/6W# during power up. 48 MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by voltage applied to VDDQ3. 66 MHz Output 0 through 3: Fixed 66-MHz outputs. Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output frequency as shown in Table 1. Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or other reference signal. Crystal Connection: An output connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. 4-way/6-way Output Select: This input can be changed after initialization and has an internal pull-up resistor. If left unconnected during power-up, the outputs are configured so that all CPU and APIC outputs are active. If it is pulled down during power-up, CPU5:6 and APIC5:6 will be disabled. Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables spread spectrum mode when held LOW. Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that requests the device to enter power down mode. Ground Connection
CPUdiv2_ 0:1
32, 31
O
3V33_0:1 REF0/ FIXAPIC#*
23, 24 9
O I/O
REF1/TEST#*
10
I/O
APIC0:6
4, 3, 1, 56, 55 53, 52 14 16, 17, 20, 21 29 6 7 26
O
48MHz 3V66_0:3 SEL133/100# X1 X2 6W/4W#*
O O I I O I
SPREAD# PWRDWN# GND
50 34 2, 11, 13, 19, 25, 28, 33, 37, 38, 45, 46, 51 8, 12, 15, 18, 22, 27 5, 30, 35, 41, 42, 49, 54
I I G
VDDQ3 VDDQ2
P P
Power Connection: Power supply for 3V33, 3V66, 48MHz, and REF output buffers, core circuitry and PLL circuitry. Connect to 3.3V supply. Power Connection: Power supply for APIC and CPU, CPUdiv2 output buffers. Connect to 2.5V supply. provides skew-controlled PCI and IOAPIC clocks synchronous to CPU clock, 48-MHz Universal Serial Bus (USB) clock, and replicates the 14.31818-MHz reference clock. All CPU, PCI, and IOAPIC clocks can be synchronously modulated for spread spectrum operations. Cypress employs proprietary techniques that provide the maximum EMI reduction while minimizing the clock skews that could reduce
Overview
The W159B is designed to provide the essential frequency sources to work with advanced multiprocessing Intel(R) architecture platforms. Split voltage supply signaling provides 2.5V and 3.3V clock frequencies operating up to 133 MHz. From a low-cost 14.31818-MHz reference crystal oscillator, the W159B generates 2.5V clock outputs to support CPUs, core logic chip set, and Direct RDRAM clock generators. It also
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W159B
system timing margins. The use of spread spectrum modulation is controlled by an external signal input. The W159B also includes power management control inputs. By using these inputs, system logic can stop CPU and/or PCI clocks or power down the entire device to conserve system power. and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is -0.5% downspread. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for the SPREAD# input pin.
Spread Spectrum Generator
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. As shown in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number
Highest Peak
Spread Spectrum Enabled
NonSpread Spectrum
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
100% 80% 60% 40% 20% 0% -20% -40% -60% -80% -100%
Frequency Shift
10%
20%
30%
40%
50%
60%
70%
80%
90%
10%
20%
30%
40%
50%
60%
70%
80%
100%
90%
Time
Figure 2. Modulation Waveform Profile
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100%
W159B
Maximum Allowed Current
Table 2. Maximum Allowed Current Max. 2.5V Supply Consumption Max. Discrete Cap Loads, VDDQ2 = 2.625V All Static Inputs = VDDQ3 or VSS 300 A 120 mA 120 mA Max. 3.3V Supply Consumption Max. Discrete Cap Loads, VDDQ3 = 3.465V All Static Inputs = VDDQ3 or VSS 500 A 160 mA 160 mA
Condition Power-down Mode (PWRDWN#=0) Full Active 100 MHz SEL133/100#=0 Full Active 133 MHz SEL133/100#=1
Table 3. Clock Enable Configuration[2, 3, 4] PWRDWN# 0 1 CPUCLK LOW ON CPUdiv2 LOW ON APIC LOW ON 3V66 LOW ON 3V33 LOW ON 48MHz LOW ON REF LOW ON OSC. OFF ON VCOs OFF ON
Table 4. Power Management State Transition Signal PWRDWN# Signal State 1 (normal operation) 0 (power down) Latency[5] 3 ms 2 PCI clocks (max.)
Timing Diagram
PWRDWN# Timing Diagram[6, 7, 8, 9, 10]
CPUCLK (internal) PCI (internal) PWRDWN# CPUCLK (external) PCI (external) VCO
Crystal Notes: 2. LOW means outputs held static LOW as per latency requirement below. 3. ON means active. 4. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs. 5. Power-up latency is when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device. 6. All internal timing is referenced to the CPUCLK. 7. The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is designed. 8. PWRDWN is an asynchronous input and metastable conditions could exist. This signal is synchronized by the W159B internally. 9. The shaded sections on the VCO and the Crystal signals indicate an active clock. 10. Diagrams shown with respect to 133 MHz. Similar operation when CPUCLK is 100 MHz.
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W159B
Absolute Maximum Ratings [11]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi.
tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.) Unit V C C C kV
Parameter VDD, VIN TSTG TA TB ESDPROT
Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5%
Parameter Supply Current IDD-3.3V IDD-2.5 VIL VIH IIL IIH IIL IIH Combined 3.3V Supply Current Combined 2.5V Supply Current Input Low Voltage Input High Voltage Input Low Current[13] Input High Current[13] SEL133/100#[13] Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.25V VOH = 1.25V Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V 3.1 70 65 100 95 145 135 3.1 45 45 Min. 65 65 Typ. 100 100 Max. 50 2.2 45 45 Min. 65 65 Typ. 100 100 Max. 50 Min. Typ. Input Low Current, SEL133/100#[13] Input High Current, CPU0:3 =133 MHz[11] CPU0:3 =133 MHz[11] GND - 0.3 2.0 160 90 0.8 VDD + 0.3 -25 10 -5 5 Max. 50 mA mA V V A A A A Unit mV V mA mA Unit mV V mA mA Unit mV V mA mA Description Test Condition Min. Typ. Max. Unit
Logic Inputs (All referenced to VDDQ3 = 3.3V)
Clock Outputs CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2) VOL VOH IOL IOH VOL VOH IOL IOH VOL VOH IOL IOH Output Low Voltage Output High Voltage Output Low Current Output High Current Output Low Voltage Output High Voltage Output Low Current Output High Current Output Low Voltage Output High Voltage Output Low Current Output High Current
48MHz, REF (Referenced to VDDQ3)
3V33, 3V66 (Referenced to VDDQ3)
Notes: 11. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 12. All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 13. W159B logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
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W159B
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5% (continued)
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[14] Load Capacitance, Imposed on External Crystal[15] X1 Input Capacitance[16] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 1.65 18 28 5 6 7 V pF pF pF pF nH Description Test Condition Min. Typ. Max. Unit
Pin Capacitance/Inductance
3.3V AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V 5%, fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[17] 3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF) Parameter f tH tL tR tF tD tJC Description Frequency High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Note 18 Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all 3V66 outputs. Measured on rising edge at 1.5V. CPU leads 3V66 outputs. 0 4.95 4.55 1 1 45 4 4 55 500 Test Condition/Comments Min. Typ. 66.6 Max. Unit MHz ns ns V/ns V/ns % ps
tSK tO fST
Output Skew CPU to 3V66 Clock Skew
250 1.5 3
ps ns ms
Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 15
Zo
Notes: 14. X1 input threshold voltage (typical) is VDD/2. 15. The W159B contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 16. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 17. Period, jitter, offset, and skew measured on rising edge at 1.5V. 18. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
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W159B
3V33 Clock Outputs, 3V33_0:1 (Lump Capacitance Test Load = 30 pF) Parameter tP tH tL tR tF tD tJC tSK tO tq fST Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew 3V66 to 3V33 Clock Skew CPU to 3V33 Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on rising edge at 1.5V[19] Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all 3V66 outputs. Measured on rising edge at 1.5V. 3V66 leads 3V33 output. Covers all 3V33 outputs. Measured on rising edge at 1.5V. CPU leads 3V33 output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 1.5 1.5 Min. 30 12 12 1 1 45 4 4 55 500 500 3.0 4.0 3 Typ. Max. Unit ns ns ns V/ns V/ns % ps ps ns ns ms
Zo
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
Note: 19. 3V33 clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
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W159B
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
2.5V AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2= 2.5V5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[20] CPU Clock Outputs, CPU0:6 (Lump Capacitance Test Load = 20 pF) CPU = 133 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 7.5 1.87 1.67 1 1 45 4 4 55 200 7.65 CPU = 100 MHz Typ. Max. Unit 10.2 ns ns ns 4 4 55 200 V/ns V/ns % ps 10 3.0 2.8 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
20
Note: 20. Period, Jitter, offset, and skew measured on rising edge at 1.25V.
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W159B
CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF) CPU = 133 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 15 5.25 5.05 1 1 45 4 4 55 250 15.3 CPU = 100 MHz Typ. Max. 20.4 Unit ns ns ns 4 4 55 250 V/ns V/ns % ps 20 7.5 7.3 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
20
APIC Clock Outputs, APIC0:2 (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Note 21 Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 1 1 45 Test Condition/Comments Min Typ 16.67 4 4 55 3 Max Unit MHz V/ns V/ns % ms
Zo
Note: 21. APIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz.
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W159B
Ordering Information
Ordering Code W159B Package Name H Package Type 56-pin SSOP (300 mils)
Package Drawing and Dimensions
56-lead Shrunk Small Outline Package O56
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
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